1. Technical Field
Various embodiments relate to a semiconductor apparatus, and more particularly, to a phase mixing circuit which mixes the phases of clocks, and a semiconductor apparatus and a semiconductor system including the same.
2. Related Art
In general, a semiconductor apparatus is configured to operate in synchronization with a clock. In order to precisely perform various complicated operations or precisely perform communication between devices electrically coupled with each other, a semiconductor apparatus uses a clock for correcting the phase thereof. By mixing phases of a plurality of clocks with different phases, the phase of the clock may be corrected.
FIG. 1 is a diagram schematically showing a configuration of a conventional phase mixing circuit 10. In FIG. 1, the phase mixing circuit 10 includes a first driver 11, a second driver 12, and an output unit 13. The first driver 11 changes the phase of a first clock CLK1 in response to control signals CODE<1:n> and inverted control signals CODEB<1:n>, and provides an output to an output node N1. The second driver 12 changes the phase of a second clock CLK2 in response to the control signals CODE<1:n> and the inverted control signals CODEB<1:n>, and provides an output to the output node N1. The output unit 13 generates an output signal MIXO from the outputs of the first driver 11 and the second driver 12.
Each of the first and second drivers 11 and 12 includes a plurality of switch inverters 20 as shown in FIG. 2. FIG. 2 shows a switch inverter 20 which may be included in the first driver 11. The switch inverter 20 includes a first switch transistor 21, a second switch transistor 22, and an inverting section 23. The first switch transistor 21 is constituted by a PMOS transistor and receives the inverted control signal CODEB<n>. The second switch transistor 22 is constituted by an NMOS transistor and receives the control signal CODE<n>. The inverting section 23 may invert the first clock CLK1 when the first and second switch transistors 21 and 22 are turned on, and output an output.
The switch inverters of the first driver 11 receive the inverted control signals CODEB<1:n> through first switch transistors, respectively, and receive the control signals CODE<1:n> through second switch transistors, respectively. The inverting sections of the switch inverters may commonly receive the first clock CLK1 and may be electrically coupled in parallel with one another. Similarly, the switch inverters of the second driver 12 receive the control signals CODE<1:n> through first switch transistors, respectively, and receive the inverted control signals CODEB<1:n> through second switch transistors, respectively. The inverting sections of the switch inverters may commonly receive the second clock CLK2 and may be electrically coupled in parallel with one another.
In the phase mixing circuit 10, the duty ratio of the output signal MIXO, in some instances, is not constant. The lack of a constant duty ratio of the output signal MIXO may be attributable to processing characteristics. For instance, when processing characteristics cause NMOS transistors to operate at a different pace than PMOS transistors, the duty ratio of the output signal MIXO may increase or decrease when compared to when the NMOS transistors and the PMOS transistors have the same processing characteristics.
FIG. 3 is a timing diagram showing operations of the conventional phase mixing circuit. FIG. 3 provides an example where each of the first and second drivers 11 and 12 includes four switch inverters and the phases of the first and second clocks CLK1 and CLK2 are mixed at the ratio of 3:1. In FIG. 3, case A shows the waveform of an output signal when the processing characteristics of NMOS transistors and PMOS transistors are the same. Case B shows the waveform of an output signal when NMOS transistors have processing characteristics that are slower than PMOS transistors. Case C shows the waveform of an output signal when NMOS transistors have processing characteristics that are quicker than PMOS transistors.
In case B, the first clock CLK1 and the second clock CLK2 are mixed with a mixing ratio of 3:1 while the first clock CLK1 has a high level and the second clock CLK2 has a low level. Because, however, the operations of the NMOS transistors are relatively slower, the actual mixing ratio is about 2.4:1, and the actual mixing ratio when the first clock CLK1 has a low level and the second clock CLK2 has a high level is about 3.6:1. Accordingly, the output signal has a delayed rising time and an early falling time in comparison with the case of A. Thus, a lower duty ratio distortion occurs.
In case C, the first clock CLK1 and the second clock CLK2 are mixed with a mixing ratio of 3:1 while the first clock CLK1 has a high level and the second clock CLK2 has a low level. Because, however, the operations of the NMOS transistors are relatively quicker, an actual mixing ratio is about 3.6:1, and an actual mixing ratio when the first clock CLK1 has a low level and the second clock CLK2 has a high level is about 2.4:1. Accordingly, the output signal has an early rising timing and a delayed falling timing in comparison with the case of A. Thus, a higher duty ratio distortion occurs.